DARPAs Chip-to-Chip Optical Interconnects (C2OI) Program

By Lisa Huff

The C2OI DARPA program is funding on-going optical components projects. Its end goal is to “demonstrate optical interconnections between multiple silicon chips that will enable data communications between chips to be as seamless as data communication within a chip.”

This program grew out of work initially done by Agilent (now Avago Technologies (AVGO)) under the DARPA Parallel Optical Network Interconnect (PONI) project. Agilent/Avago developed a 30 Gbps transmitter (2.5 Gbps/lane) that was eventually standardized as the SNAP-12.

IBM (with help from Avago) extended the work originally done by Agilent/Avago into inter-chip connections and in 2009 achieved optical interconnection with 16 parallel lanes of 10G. By early 2010, IBM was extending this work into board-to-board applications which resulted in the new Avago MicroPOD™ product that was specifically designed for IBM’s POWER7™ supercomputer.

While it was designed for HPC server interconnects, the MicroPOD could be used for on-board or chip-to-chip interconnects as well. As mentioned in previous posts, the devices use a newly designed miniature detachable connector from US CONEC called PRIZM™ LightTurn™. The system has separate transmitter and receiver modules that are connected through a 12-fiber ribbon. Each lane supports up to 12.5 Gbps. It uses 850nm VCSEL and PIN diode arrays. The embedded modules can be used for any board-level or I/O-level application by either using two PRIZM LightTurn connectors or one PRIZM LightTurn and one MPO.

While MicroPOD is targeted at high-density HPC environments, a natural expansion of its market reach would be into switches and routers in high-density Ethernet data center environments. While this may not happen in the next few years, for me it looks like it could be a more cost-effective solution than say a 40G serial one.